An Encoded Photodetector Array for High-Frame-Rate Compressed Sensing and Computational Imaging

Modern imaging technology, by exposure and subsequent readout from image sensors, has limited the existing frame rate in real-time scenes. In this article, we present an architecture based on computing in sensor array that can achieve higher frame rates than conventional cameras. This approach fuses the architecture with neural network algorithms for compressed sensing and computational imaging. It achieves a mean squared error of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{2}}$ </tex-math></inline-formula> with fewer weights and sampling numbers (10%–40% of original data). It samples lower data to reconstruct images through fast recovery with an elapsed time of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$100~\mu $ </tex-math></inline-formula>s. The feasibility has been verified through the encoded photodetector array chip consisting of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\times 16$ </tex-math></inline-formula> dual-gate silicon photodiodes. This type of chips represents a highly promising technology for constructing image sensors that deliver high-speed imaging capability of >10000 frames/s, which may also show potential superiority in terms of noise resistance and dynamic range.