A Miniaturized DC-110-GHz Attenuator Using Inductive π-Type Topology in 0.13-μm CMOS SOI

This letter presents an ultrawideband miniaturized attenuator based on an inductive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pi $ </tex-math></inline-formula>-type topology. The proposed topology absorbs the parasitic capacitance as a part of the designed network and avoids using bulky interstage inductors for matching. Extended operational bandwidths are obtained in both reference and attenuation states for each attenuation cell. Fabricated with a high-performance 0.13-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m CMOS silicon on insulator (SOI) process, the four-bit attenuator achieves an insertion loss (IL) of 0.8–2.1 dB and an rms amplitude/phase error of <0.36 dB/5.4° over the dc-110 GHz. Its core area is only 0.0034 mm2, making it the smallest reported ultrawideband attenuator to date.