A Quick Response Method for Higher-priority Interrupts Based on the RISC-V Architecture

Abstract: To accelerate the quick response of CPUs in real-time application fields for higher-priority interrupts, this paper presents a quick response method for higher-priority interrupts based on RISC-V. After the CPU responds to an interrupt and before the first instruction of the interrupt processing function flows through the last stage of the multi-level pipeline, the global interrupt enable remains open. During this period, the hardware actively determines whether a higher-priority interrupt arrives. If there is a higher-priority interrupt waiting to be processed, the processing of the current interrupt will be abandoned, the hardware pipeline will be refreshed, and the higher-priority interrupt will be responded to preferentially. This interrupt processing method enables interrupts that arrive later in time but have a higher-priority to be processed preferentially. Thus, it can meet the scenarios where the CPU has higher requirements for the response time of higher-priority interrupts.