Design and FPGA Implementation of Relative Dynamics Measurement Techniques for Satellite Communication Systems

Performance of a satellite communication receiver is greatly affected by the relative dynamics scenario. Relative dynamics is related to the variable motion between communication source and destination systems. It encompasses relative acceleration and relative jerk. The paper presents the phase error-based measurement techniques for relative dynamics. Binary Phase Shift Keying (BPSK) demodulator is considered for development and verification of the techniques. Paper describes the requirement and design of 3rd order BPSK demodulator for measurement and handling relative jerk. System level simulation is carried out for different scenario. Design is coded in VHDL and realized on the Xilinx platform. Application of developed system in adaptive signal processing based BPSK demodulator is also dealt in detail.