Digital readout integrated circuit for small pixel infrared focal plane arrays

This paper proposes a digital readout integrated circuit (DROIC) for a small pixel MW IRFPA application with a high signal-to-noise ratio (SNR). The storable charge should be substantial enough to maintain a high SNR. A tiny direct injection structure is used for a 7.5 µm pixel pitch. Second, MOSFET and MIM capacitors are employed for integral capacitance to achieve high well capacity. Furthermore, the well capacity issue is addressed by sequentially sharing a bigger capacitor between every two pixels of the arrays. The pixel signal is transferred to the column-level ADC for quantification. DROIC's ADC supports 12 or 13-bit resolution settings to choose from. Following conversion, the digital data of the signal is transferred to the off-chip via multiple output channels. The simulation indicates that the DROIC noise is 1.26 LSBrms at 77K, and the entire well capacity can reach 0.75Me- and 1.5Me- (at 1×2 binning mode), which is advantageous for NETD. The simulation shows that the suggested DROIC is suitable for small-pixel pitch infrared FPAs.