A Novel Design Technique for Enhanced Security and New Applications of Ferroelectric-Based Non-Volatile SRAM

Static Random Access Memories (SRAM) are fast and efficient circuits used as the main working memory of processing units. However, associating these volatile memories with external non-volatile memories leads to energy consumption and area penalties, while leading to security issues. Ferroelectric-based NVSRAMs are one of the most promising ways of combining the high efficiency of SRAMs with non-volatile operations to tackle these challenges. In this work, several design parameters of the bitcell are optimized to ensure error-less data transfer between 6T SRAM internal nodes and 4 ferroelectric capacitors (4C). The presented 6T4C bitcell presents STORE and RECALL energies of 161fJ/bit and 27fJ/bit, respectively, and STORE and RECALL times of 480ns and 245ns, respectively. A high reliability is achieved from −40°C to +85°C for SS, TT and FF fabrication corners. The integration of the four FeCAPs in the bitcell leads to a 46% area overhead, a 94% WRITE time degradation, and a 32% WRITE energy increase. However, an increase of less than 0.5% in both READ time and energy has been observed. A previously developed Fast-Erase system has also been integrated for countering cold-boot attacks. Combining design optimizations and Fast-Erase technique ensures cold-boot attack immunity of the memory and enables error-less RECALL with WRITE operations between STORE and RECALL, leading to new use-cases of NVSRAM circuits.