Sparsepipe: Sparse Inter-operator Dataflow Architecture with Cross-Iteration Reuse
Sparse Tensor Algebra (STA) applications are limited by data movement and can benefit from better data reuse. Prior research has focused on intra-operator data reuse, such as better dataflow or caching technique for a single STA operation, missing other reuse opportunities at the application level. By expressing STA applications as sparse tensor dataflow graphs, we first identify two unexplored inter-operator data reuse opportunities: 1) producer-consumer reuse and 2) cross-iteration reuse. Producer-consumer reuse combines multiple operations to reduce data movement for intermediate results. Cross-iteration data reuse, a new opportunity identified in this paper, reduces the data movement for the shared sparse data (e.g., graph) across iterations. We then propose Output-stationary-_Element-wise-Input-stationary (OEI) dataflow, a novel dataflow to capture both reuse opportunities in STA applications, and Sparsepipe, a sparse dataflow architecture to support the OEI dataflow and maximize data reuse. Evaluation results show that Sparsepipe with OEI dataflow is 19.82×/4.65× faster than CPU/GPU and 1.77× faster than an ideal sparse accelerator that cannot exploit inter-operator reuse.
Authors
- Hung‐Wei Tseng (ORCID: https://orcid.org/0000-0001-8383-5203)
- Po-An Tsai (ORCID: https://orcid.org/0000-0003-4561-6450)
- Yunan Zhang (ORCID: https://orcid.org/0009-0006-4567-2849)
Institutions
- University of California, Riverside (US)
- Nvidia (United States) (US)
Publication Details
- Published
- 2024-11-02
- DOI
- https://doi.org/10.1109/micro61859.2024.00090
- Citations
- 2
- Primary Topic
- Distributed and Parallel Computing Systems
- Type
- article
- Field-Weighted Citation Impact
- 0.70
Funders
- University of California, Riverside