An Educational Tool to Analyze the Hardware/Software Integration in RISC-V Systems

The analysis and verification of the integration of hardware and software components is challenging. Traditional HDL simulators, which are often slow and provide low-level analysis tools, are not always effective for simulating the software component of processor-based systems. This work presents an interactive co-simulation framework that enhances students’ understanding of computer architecture concepts typically obscured by hardware intricacies. Our framework facilitates a unified environment for iterative design, enabling detailed analysis and generation of reports and traces to identify system performance and bottlenecks. By prioritizing analysis features over performance, our framework serves as a valuable tool for educational purposes and comprehensive examination of system interactions.