128-Bit LFSR-Based Counter with Backward Carry Propagation

A high-speed counter is a device that is used to accurately count the events in a very fast manner. This design concept presents an LFSR referring to a Linear Feedback Shift Register-based counter with Backward Carry Propagation consisting of three stages resulting in a high counting rate due to constant delay. The first stage is implemented with the LFSR State Extension counter which covers all 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> states by making use of the State Extension counter which is integration of State Detection circuit and Galois Linear Feedback Shift Register. The second stage is the BCP counter referring to Backward Carry Propagation which is used to achieve both binary count and constant delay and it is followed by the third stage, which is the Conventional Binary counter. The LFSR State Extension circuit drives the counter and sets the counting rate maintaining constant delay. From this, we can say that speed is independent of the size of the counter. The proposed architecture is simulated and synthesized in Cadence Genus using 90nm CMOS technology with a supply voltage of 1.8V. It is operating at 2.15GHz clock frequency.