A Novel High Speed 2-Step TDC-Based All-Digital DLL for DDR SDRAM Applications

In sequential digital systems both Delay Locked Loops (DLLs) and the Phase Locked Loops (PLLs) are utilized for enhanced timings, i.e., to reduce the detrimental effects of distortion and instability in the circuit. An effective DLL structure with a linear delay feature has been proposed in this work. Function is accomplished by altering traditional hardware architecture. A high-speed design for All-Digital Delay-Locked Loop (ADDLL) appropriate for DDR1-DDR5 applications has been done. The suggested architecture offers the features with synchronous mirror delay and Delay Locked Loop (DLL) in a single design. TDCs are common circuits in several applications demanding final time calculations; this study offers a broad range TDC-based All-Digital Delay lock loop (AD-DLL) that is ideal for DDR usage. The AD-DLL has been implemented using 90 nm standard CMOS library at 1.2 V supply. The working range obtained from measurement results of proposed AD-DLL is 1.7 GHz to 5GHz.