Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory

Hardware Transactional Memory (HTM) offers the opportunity to ease parallel programming. However, driven by hardware limitations, commercial implementations eschew the complexity involved in early sophisticated proposals from academia, and, among other things, opt for simple conflict resolution policies that inevitably increase transaction aborts. To increase thread level parallelism, previous works propose conflict resolution schemes that, instead of aborting, add a second level of speculation consisting in using not-yet-committed data from another transaction. This policy, which we refer to as requester-speculates, has not yet been considered in the context of the kind of best-effort HTM support provided by commercial processors. This work proposes CHAining TransactionS (CHATS), a simple yet effective realization of the requester-speculates con-flict resolution policy in which cyclic dependencies between transactions are avoided and the commit ordering respects the dependencies that transactions make once speculative values are communicated. The ultimate result is a best-effort HTM implementation that forces a partial order between transactions in a way that ensures effective utilization of forwarded data and that gets away from the complexity of previous proposals. Simulations using gem5 demonstrate the effectiveness of CHATS in both commercial-like setups and academic state-of-the-art best-effort systems (22% and 16% reduction in execution time, on average, respectively). These improvements are achieved by requiring less than 280 bytes of extra storage.

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Publication Details

Published
2024-11-02
DOI
https://doi.org/10.1109/micro61859.2024.00067
Citations
1
Primary Topic
Distributed systems and fault tolerance
Type
article
Field-Weighted Citation Impact
0.35

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article

Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory

Ricardo Fernández‐Pascual, Manuel E. Acacio, Víctor Nicolás-Conesa, Alberto Ros et al.
1 citations
Distributed systems and fault tolerance
0.35
article

Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory

Ricardo Fernández‐Pascual, Manuel E. Acacio, Víctor Nicolás-Conesa, Alberto Ros, Rubén Titos-Gil
article en
1 citations

Abstract

Hardware Transactional Memory (HTM) offers the opportunity to ease parallel programming. However, driven by hardware limitations, commercial implementations eschew the complexity involved in early sophisticated proposals from academia, and, among other things, opt for simple conflict resolution policies that inevitably increase transaction aborts. To increase thread level parallelism, previous works propose conflict resolution schemes that, instead of aborting, add a second level of speculation consisting in using not-yet-committed data from another transaction. This policy, which we refer to as requester-speculates, has not yet been considered in the context of the kind of best-effort HTM support provided by commercial processors. This work proposes CHAining TransactionS (CHATS), a simple yet effective realization of the requester-speculates con-flict resolution policy in which cyclic dependencies between transactions are avoided and the commit ordering respects the dependencies that transactions make once speculative values are communicated. The ultimate result is a best-effort HTM implementation that forces a partial order between transactions in a way that ensures effective utilization of forwarded data and that gets away from the complexity of previous proposals. Simulations using gem5 demonstrate the effectiveness of CHATS in both commercial-like setups and academic state-of-the-art best-effort systems (22% and 16% reduction in execution time, on average, respectively). These improvements are achieved by requiring less than 280 bytes of extra storage.

Universidad de Murcia (ES)
H2020 European Research Council
Openalex Percentile: Top 36%
Distributed systems and fault tolerance
0.35
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Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory — Ricardo Fernández‐Pascual, Manuel E. Acacio, et al. · (2024) | TGRS Research Map | TGRS