Low Power Network-on-Chip Architecture Design Technique

In the evolving landscape of many-core architectures, the Network on Chip (NoC) emerges as a pivotal inter-connection framework, accommodating the escalating number of cores on a single chip. Despite its widespread adoption, power consumption remains a critical challenge, significantly influenced by factors such as topology, bit toggling, and routing algorithms, with bit-switching power being a predominant concern. In this work, we have proposed an innovative technique in the cores aimed at reducing the power consumption of the NoC. To calculate our method's area, time, and power consumption, we have synthesized it on a Xilinx Virtex-7 FPGA board. We have modified the Noxim open-source simulator to validate our approach using synthetic traffic. Empirical results demonstrate a 29.64% reduction in dynamic power consumption and a 29.09% improvement in switching activity for the average case (Mode 1) traffic scenario.