Adaptable FWHW Formal Co-Verification of SoC RISC-V Components

The increasing shift towards the RISC-V open-source instruction set architecture requires the development of new design techniques. In recent years, it has been demonstrated that RISC-V designs can be generated in a modular and scalable manner by utilizing metamodeling techniques. However, verifying these designs presents a significant challenge, because the verification must consider both Register Transfer Level (RTL) components and firmware components such as drivers. Furthermore, the interaction between firmware and hardware components is susceptible to various issues, including incorrect transaction sequences, synchronization problems, encoding mismatches, and reserved values. Traditionally, verifying the interaction between hardware and firmware requires simulation/emulation tools and verification engineers with expertise in both firmware and hardware. To overcome these challenges, this paper introduces an automated formal verification approach for FWHW Co-verification of peripherals such as timers and interrupt controllers, and their respective drivers in generated RISC-V designs. This verification process employs formal verification methods. This methodology enables the detection of bugs in both hardware and firmware because it consists of the verification of individual components that can be reused later in the integration process. By implementing this methodology in the early design stages, developers can identify and address potential issues more efficiently and avoid later corrections.