A Low-Power Linear Phase Interpolation-Based Delay Line in 12nm FinFET Technology

A novel low-power high-linear phase interpolation-based delay line in 12nm FinFET technology is detailed in this paper. The proposed delay line exhibits 50% improvement in terms of power consumption compared to the previous work. In addition, the presented architecture to the best of our knowledge is the most efficient delay line for fine tuning in advanced technology nodes due to the low complexity and complete controllability over resolution, delay range and target frequency. The analysis in this paper indicates that the input slew rate plays an indispensable role in the linearity of the delay line. Consequently, two identical resistors are added to the input of the phase interpolator unit to decrease the slew rate. This approach significantly improves the linearity over a wide frequency range. The proposed delay line dissipates 0.56 mW from a 0.8 V supply voltage and 5 GHz operating frequency.