FVDCLS: Functional Verification of RISCV Based Dual-Core Lockstep Feature Using Fault Injection Mechanism

This paper presents the framework to verify RISCV based Dual-Core Lockstep (DCLS), a feature that enhances the fault tolerance in processors. The DCLS feature, when two identical processors run in parallel, effectively detects the error and rolls back the core operations to a previously known state. The purpose-built fault injection mechanism is developed using universal verification methodology (UVM) and contains two modules: i) The fault injector (FI), ii) The virtual comparator (VC). The FI systematically injects the error in one of the core's internal states by flipping one or multiple bits. While the VC stores the internal states of both the RISCV cores on each clock cycle and reports the anomaly, if detected. The SweRV EH1 (an open-source RISCV core) is customized to add the DCLS functionality and later Google RISC-V DV test suite is used to validate the proposed FVDCLS. In total, nine different verification scenarios are developed consisting of transient and permanent errors using FI module. For all these test scenarios the VC compared hundred different internal state signals/registers. The result shows that the FVDCLS successfully detected and reported all the mismatches. Moreover, the FVDCLS incorporates an error debugging module that generates the summary of conducted test particularly, the type of fault injected, the number of errors detected, and the injected fault coverage. The proposed FVDCLS is portable and configurable; therefore, can be seamlessly integrated with any processor (with DCLS feature) under test.