A Hardware Architecture for Frequency-Domain Image Processing Based on Split-Radix 2-4 FFT

Fast Fourier Transform (FFT) is a necessary and widely used algorithm in frequency-domain image processing, and the iterative calculation of 2D FFTs and iFFTs (inverse Fast Fourier Transform) is commonly applied. The general sequence of the global calculations often implies reiterative processes of data loading and storing. On the other hand, the detection-in-frequency split-radix 2-4 FFT has advantages in terms of resources and latency, compared to the radix-2 or the radix-4 schemes. In this way, a hardware architecture for frequency-domain image processing is proposed here, where a split-radix 2-4 multi-path delay commutation architecture (MDC) FFT structure with four parallel inputs and outputs is designed to achieve $100 \%$ resource utilization. In addition, a dynamic ping-pong switching between the FFT and the iFFT is designed to implement a non-stalled stream on calculation by means of a feedback path without reloading data. Furthermore, as for the conjugate symmetry of the transfer function, the processing order of the image is designed to reduce the number of calculations or data loading. Comparing with other architectures, the proposed one requires less buffers, complex multiplications and complex additions, whereas it also provides a low latency and a wide range of sequence lengths. In this way, in a frequency-time domain processing for an image, only 2 loads and 2 stores are required per iteration because of the dynamic ping-pong switching.