MCS-NTT: Multi-Chip System Design for NTT Acceleration

Hardware implementations of Number Theoretic Transform (NTT), especially ASIC designs, have provided significant speed improvements for lattice-based cryptography schemes used by Post-Quantum Cryptography (PQC) and Fully Homo-morphic Encryption (FHE). While most of the existing solutions are tailored for fixed polynomial degrees and modulus sizes, both parameters can vary considerably depending on the application and scheme. Toward this end, our paper introduces MCS-NTT, the first hardware architecture for NTT acceleration that is based on a multi-chip-system (MCS) design approach. Our proposed solution provides scalability to existing NTT accelerators by seamlessly integrating multiple accelerator units around an FPGA-based centralized unit. This configuration effectively establishes a customized star network tailored to meet specific use cases. The experimental results indicate that MCS-NTT offers considerable flexibility with better performance metrics.