Behavioral Simulation of Relative Timed Asynchronous Circuits

Relative Timed design represents timing constraints in an integrated circuit as mathematical equations. This differs from current state of the art integrated circuit design methodologies and electronic design automation tools which employ a finite state machine methodology by using a clock to implement circuit timing. This paper presents a behavioral model for relative timing constraints that enables simulation and evaluation of relative timed circuits written in behavioral Verilog. The model enables the source behavioral Verilog to be directly synthesized into relative timed circuits. The model provides support for rapid design exploration, architectural timing experiments, design validation, and multi-mode behavioral and structural simulations. Experiments show a 50 x speedup over current Verilog designs that require a structural implementation.