Test mode selection and data I/O by means of a new Scan-based interface

Digital logic is typically tested by means of the scan chain methodology. Scan test procedures often need to be applied with different configurations (e.g., selectively activating certain clock domains or bypassing memory cores), which usually are dynamically set by means of functional or dedicated interfaces (e.g., IEEE 1149.1 JTAG). In addition, it may be useful to read some functional device data during the scan operation. This paper describes a novel approach for accessing in write or read mode some specific signals during the scan test procedure, employing the same protocol used for controlling scan chains and thus easing test generation and application.