BiDSRS: Resource Efficient Real Time Bidirectional Super Resolution System for FPGAs

The burgeoning field of computer vision applications and visual display devices has propelled the exploration of super resolution (SR) techniques, drawing attention from both academia and industry. Field programmable gate arrays (FPGAs) have emerged as a favored platform for implementing intricate algorithms, given their energy efficiency and parallel computing capabilities. However, the demand for real-time SR systems employing deep learning poses challenges due to their resource-intensive nature, particularly when targeting edge or resource-constrained devices which creates a pressing need for energy and resource-efficient SR solutions. Besides, conventional SR methods predominantly focus only on upscaling or downscaling images or videos within a system. To bridge this gap, this paper proposes BiDSRS, a resource-efficient real-time SR system tailored for FPGAs, utilizing a modified bicubic interpolation method. In addition, BiDSRS facilitates scaling in both directions, allowing for upscaling and downscaling of images or videos. Evaluation conducted on the Xilinx ZCU 102 FPGA board demonstrates significant resource savings, achieving a reduction of 46x LUT, 31x BRAM, and 41x DSP utilization compared to state-of-the-art DNN-based SR systems, albeit with a throughput trade-off of 0.25x. Similarly, compared to leading algorithm-based SR systems, BiDSRS achieves savings of 23x LUT, 5x BRAM, and 4x DSP resources, albeit with a throughput trade-off of 0.5x. Despite a reduced throughput of 4K@30 Frame Per Second (FPS), BiDSRS substantially decreases FPGA resource utilization for video SR tasks, offering support for sustainable and energy-efficient computing systems.