A Low-Cost Bit-Serial Hardware Architecture and FPGA implementation of Spiking Neural Network

This paper presents a low-cost bit-serial spiking neural network architecture that employs a binary signed-digit (BSD) number system, which relies on the most significant digit-first (MSD-first) serial addition. A pipeline online bit-serial adder is proposed. The online bit-serial adder performs addition with a limited carry chain and variable length precision. The experiments are conducted using Xilinx Zynq-7000 FPGA. The proposed bit-serial architecture with the adder circuits reduces FPGA resources against bit-parallel implementation. The benefit of the proposed bit-serial architecture is that it allows high throughput computing with scalable precision of the leak-integrate-and-fire (LIF) neural model. The experimental results highlight the suitability of the proposed architecture for deployment in resource-constrained FPGA-based embedded systems.