Capacitive Deep Trench Interface Characterizations and Dark Current Modeling for Photogate Pixels
In a CMOS image sensor, the total dark current (DC) is the sum of several contributions that are difficult to discriminate, even if activation energies are extracted. For example, when considering the interface generation, there may still be ambiguities about which interface, whether the front-side, back-side, or trench isolation is dominant. Electrical characterizations on test structures are powerful tools for investigating specific interfaces and providing complementary information, such as passivation quality. In this work, chemical and field-effect passivation are studied using capacitance-voltage measurements on a dedicated test structure. Quantitative results are obtained, enabling the computation of DC based on the Shockley-Read–Hall (SRH) formalism. This model, which depends on the voltage applied to the trench, fits direct DC measurements.
Authors
- Stéphane Ricq
- Olivier Marcelot (ORCID: https://orcid.org/0000-0003-1829-3465)
- Thomas Dalleau
- Pierre Magnan (ORCID: https://orcid.org/0000-0003-3122-7163)
- Samuel Tlemsani
- J.-P. Carrere
- Emilie De Pretto
Institutions
- STMicroelectronics (India) (IN)
- STMicroelectronics (France) (FR)
Publication Details
- Journal
- IEEE Transactions on Electron Devices
- Published
- 2024-12-03
- DOI
- https://doi.org/10.1109/ted.2024.3501255
- Primary Topic
- CCD and CMOS Imaging Sensors
- Type
- article
- Field-Weighted Citation Impact
- 0.00