Silicon photonics convolution accelerator based on coherent chips with sub-1 pJ/MAC power consumption

Artificial intelligence (AI), owing to its substantial computing demands, necessitates computing hardware that offers both high speed and high power efficiency. A silicon photonic integrated circuit shows promise as a hardware solution due to its attributes, including high power efficiency, low latency, large bandwidth, and complementary metal–oxide–semiconductor (CMOS) compatibility. Here, we propose a silicon photonic convolution accelerator (SiPh-CA) and experimentally realize a prototype with sub-integrated coherent transmit–receive optical sub-assemblies (sub-IC-TROSAs). The prototype, compared to a previous IC-TROSA-based convolution accelerator, achieves almost the same performances of 1.024 TOPS/channel and 96.22% inference accuracy when it processes neural networks for image recognition, using half the numbers of the modulators and the drivers with which over 1/3 chip footprint and 37.01% power consumption are reduced. By incorporating a broadcasting scheme based on splitters and combiners, the approach can efficiently process multiple convolutions in parallel, achieving several tera operations per second. This scalability feature allows the SiPh-CA to process complex AI and high-performance computing tasks.