Implementation and Optimization of Polyphase Channelization Using VITIS HLS

Wideband digital channelization technique is widely used in software defined radio, radar signal detection, particle physics, astrophysics and other applications. As a commom form in digital signal channelization, polyphase filtering is characterized by high parallelism which is suitable for implementation in Field Programmable Gate Arrays (FPGA). Based on the High-Level Synthesis (HLS), this paper presents a method of parametrically generating hardware implementation of polyphase channelization. High-Level Synthesis promises to generate RTL-level design from high-level language description, reducing design period, raising productivity and providing more flexibility. Using Vitis HLS tool, we completed C synthesis, verification and implementation of main HLS modules: Polyphase Filter Module and IFFT Inverse Module. The Radix-2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> architecture is used to design FFT processor. The implementation of a 16-channel, 4GHz signal sample rate polyphase channelizer design runs at 500MHz speed, consuming 3.72% of the LUTs and 5.96% of the DSPs in the XCVU3P SoC. Additional implementation of 64-channel channelizer demonstrates the flexibility of the HLS design.