Implementation of Channel Deinterleaver for 5G NR PUCCH Channel

This study focuses on designing a 3GPP-compliant channel deinterleaver for the 5G new radio (NR) physical uplink control channel (PUCCH) for field programmable gate array (FPGA). The PUCCH transmit chain employs a complex triangular structure for channel interleaving which typically requires nested ‘for’ loops, while the channel deinterleaver in the receive chain has to perform the reverse operation using LLRs, which requires handling multiple bits, thereby increasing complexity. We present a novel algorithm for FPGA implementation of the channel deinterleaver with reduced complexity by replacing the nested ‘for’ loop with a single ‘for’ loop and conditional variable increment. Our design is benchmarked using a 2-tier testing strategy with the Matlab 5G NR toolbox, with test vectors covering all configurations. Our FPGA implementation demonstrates that the designed channel deinterleaver completes its operation within a slot duration of 5G NR with minimal resource utilization.