Evolution of the liquid/solid interface roughness in Si1-xGex layers processed by nanosecond laser annealing

• The liquid–solid (l/s) interface roughness profiles of laser-annealed relaxed- and strained-SiGe layers have been investigated with a quantification methodology based on STEM-HAADF micrographs. • Increasing the boron doping and reducing thereby the compressive strain leads to a decrease of the l/s roughness. • In the surface melt regime, deeper melted nano-islands are formed when increasing the Ge content, resulting in an indirect l/s roughness increase. • Reducing the laser pulse duration significantly lowers the l/s interface roughness and avoid the formation of defects. • In thick layer, extreme laser conditions induce a cellular surface morphology formed by buried Ge-rich walls. Pulsed laser annealing is a relevant alternative to conventional thermal processes for future technology nodes as it enables the application of a fast and local thermal budget. Such high-energy process can lead to the formation of a liquid phase that recrystallizes upon heat dissipation, through a high velocity liquid/solid interface moving towards the surface. Here, we report on the evolution of the liquid/solid interface roughness and its influence on the crystallinity of Si 1-x Ge x layers depending on multiple parameters (strain state, doping level, Ge content, and pulse duration). This has been conducted with a roughness quantification method based on cross-section STEM-HAADF micrographs. It has been established that the liquid/solid roughness can be decreased by: (i) a compressive strain decrease, (ii) the use of short duration laser pulses or (iii) a reduction of the initial Ge content. The Ge content and strain must correspond to suitable values for optimized MOSFET performances. Consequently, strain and pulse duration were found to be pertinent levers for liquid/solid interface roughness reduction. Increasing the amount of boron atoms in s-Si 1-x Ge x :B/Si systems is another relevant strategy, as compressive strain decrease would then be associated with a beneficial contact resistance lowering in the source-drain regions of p-type MOSFET devices.