Variation-aware analysis of buried-channel-array transistors (BCATs) in scaled DRAM: insights from 3D quasi-atomistic simulations

Abstract As dynamic random access memory (DRAM) feature sizes continue to scale down, optimizing performance requires the evolution of architectures such as the buried-channel-array transistor (BCAT). Diminutive DRAM cell dimensions have increased susceptibility to variation, necessitating comprehensive simulations considering both systematic and random aspects. This study employs a three-dimensional quasi-atomistic model to implement surface random variations and investigates systematic structural variation induced by rounding between saddle-fin and source/drain regions. The impact on BCAT performance is analyzed using the standard deviation (SD) of output parameters, simultaneously simulating surface and structural aspects. Results show that increased surface roughness corresponds to increased SD, while alterations in structural variation, particularly channel and sidewall curvature, influence both mean and SD. Increased curvature leads to decreased threshold voltage and increased current levels. This simulation approach enables detailed estimation of variation distribution in BCATs, providing valuable insights for optimizing design and fabrication processes, ultimately enhancing DRAM performance and reliability. The findings highlight the importance of considering the interplay between surface and structural variations in advanced memory devices.