A Broadband <i>Gm</i>-Boosted Active Feedback CMOS Low-Noise Amplifier for Low- and Mid-Band 5G Applications
An inductor-less wideband LNA is designed for a 5G midband applications. The noise reduction technique is proposed to address the trade-off between input return loss <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(S_{11})$ </tex-math></inline-formula> and noise figure (NF). The proposed structure combines self-cascode transistors and composite transistors to increase <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> without consuming additional current, which can improve NF and linearity. In contrast to conventional noise cancellation techniques, the proposed technique improves the NF by reusing current without a path for noise cancellation. The proposed LNA is designed with a 0.13-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m CMOS process and measured. In experiments, the proposed LNA shows a power gain <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(S_{21})$ </tex-math></inline-formula> of 21.5 dB over a 3dB bandwidth of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.01\sim 1$ </tex-math></inline-formula>.7 GHz, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S_{11}$ </tex-math></inline-formula> is less than −10 dB over the range 0.01~2 GHz. Also minimum NF of proposed LNA is 1.1 dB. In case of the linearity, the proposed LNA shows an input-referred third-order intercept point (IIP3) of −7.5 - 2.3 dBm. The power consumption is 9.1 mW from a 1.3 V supply voltage and chip area is 0.18 mm2.
Authors
- D.Y. Kim (ORCID: https://orcid.org/0009-0005-4706-0056)
- Donggu Im (ORCID: https://orcid.org/0000-0003-2892-6254)
- Jong‐Won Park
Institutions
- Jeonbuk National University (KR)
Publication Details
- Journal
- IEEE Transactions on Circuits & Systems II Express Briefs
- Published
- 2024-11-29
- DOI
- https://doi.org/10.1109/tcsii.2024.3508773
- Citations
- 2
- Primary Topic
- Radio Frequency Integrated Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.42
Funders
- National Research Foundation of Korea
- Institute for Information and Communications Technology Promotion