Enhanced Electrical Performance of InAs Nanowire Field-Effect Transistors Based on the Y<sub>2</sub>O<sub>3</sub> Isolation Layer

Nanowire (NW) field-effect transistors (FETs) have great potential in next-generation integrated circuits. InAs NWs are suitable for N-type transistors because of their excellent electrical properties. However, unlike the Si/SiO<sub>2</sub> system, the loose and defective native oxide of InAs is unable to passivate the channel surface and serve as an efficient isolation layer (IL) in the gate stack. Here, we, for the first time, demonstrate that using a stable dielectric Y<sub>2</sub>O<sub>3</sub> to replace the native oxide IL can effectively passivate the NW surface, isolate the channel surface from high-k HfO<sub>2</sub>, and improve the electrical properties of InAs NW FETs significantly. First, top-gate devices with Y<sub>2</sub>O<sub>3</sub> IL outperform the devices with native oxide or chemically generated oxide of InAs as the IL, exhibiting a small subthreshold swing (SS) of 77 mV/dec, a large on-off ratio, a high field-effect mobility (μ<sub>FE</sub>) of 1845 cm<sup>2</sup>/V·s, and an extremely low interface trap density (<i>D</i><sub>it</sub>) of 9.1 × 10<sup>11</sup> eV<sup>-1</sup> cm<sup>-2</sup>. Double-gate FETs with Y<sub>2</sub>O<sub>3</sub> IL also show excellent gate control (drain-induced barrier lowering (DIBL) down to 35 mV/V) and a high μ<sub>FE</sub> of 2711 cm<sup>2</sup>/V·s (the highest in the multigate structure). In addition, InAs NW FETs with Y<sub>2</sub>O<sub>3</sub> IL show greater stability after long-term air exposure than those with native oxide IL, demonstrating retained on-off ratio, DIBL, transconductance, and even smaller SS (from 89 to 77 mV/dec). Finally, the results of low-temperature measurement suggest that Y<sub>2</sub>O<sub>3</sub> IL can effectively improve interface qualities. Our results indicate that Y<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub> InAs NW FETs have great potential in digital units of integrated circuits for future nodes. Our strategy for improving the interface between InAs NW and the dielectric layer is also valuable for other III-V NW devices.

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Journal
ACS Applied Materials & Interfaces
Published
2024-11-29
DOI
https://doi.org/10.1021/acsami.4c18313
Citations
1
Primary Topic
Nanowire Synthesis and Applications
Type
article
Field-Weighted Citation Impact
0.18

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Enhanced Electrical Performance of InAs Nanowire Field-Effect Transistors Based on the Y2O3 Isolation Layer

Yifan Jiang, Bingjie Wang, Tong Li, Qing Chen et al.
1 citations
ACS Applied Materials & Interfaces
Nanowire Synthesis and Applications
0.18
article

Enhanced Electrical Performance of InAs Nanowire Field-Effect Transistors Based on the Y2O3 Isolation Layer

Yifan Jiang, Bingjie Wang, Tong Li, Qing Chen, Shuo Li, Jiamin Tian
article en
1 citations

Abstract

Nanowire (NW) field-effect transistors (FETs) have great potential in next-generation integrated circuits. InAs NWs are suitable for N-type transistors because of their excellent electrical properties. However, unlike the Si/SiO<sub>2</sub> system, the loose and defective native oxide of InAs is unable to passivate the channel surface and serve as an efficient isolation layer (IL) in the gate stack. Here, we, for the first time, demonstrate that using a stable dielectric Y<sub>2</sub>O<sub>3</sub> to replace the native oxide IL can effectively passivate the NW surface, isolate the channel surface from high-k HfO<sub>2</sub>, and improve the electrical properties of InAs NW FETs significantly. First, top-gate devices with Y<sub>2</sub>O<sub>3</sub> IL outperform the devices with native oxide or chemically generated oxide of InAs as the IL, exhibiting a small subthreshold swing (SS) of 77 mV/dec, a large on-off ratio, a high field-effect mobility (μ<sub>FE</sub>) of 1845 cm<sup>2</sup>/V·s, and an extremely low interface trap density (<i>D</i><sub>it</sub>) of 9.1 × 10<sup>11</sup> eV<sup>-1</sup> cm<sup>-2</sup>. Double-gate FETs with Y<sub>2</sub>O<sub>3</sub> IL also show excellent gate control (drain-induced barrier lowering (DIBL) down to 35 mV/V) and a high μ<sub>FE</sub> of 2711 cm<sup>2</sup>/V·s (the highest in the multigate structure). In addition, InAs NW FETs with Y<sub>2</sub>O<sub>3</sub> IL show greater stability after long-term air exposure than those with native oxide IL, demonstrating retained on-off ratio, DIBL, transconductance, and even smaller SS (from 89 to 77 mV/dec). Finally, the results of low-temperature measurement suggest that Y<sub>2</sub>O<sub>3</sub> IL can effectively improve interface qualities. Our results indicate that Y<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub> InAs NW FETs have great potential in digital units of integrated circuits for future nodes. Our strategy for improving the interface between InAs NW and the dielectric layer is also valuable for other III-V NW devices.

ACS Applied Materials & InterfacesVol. 16(49)
Peking University (CN)
National Natural Science Foundation of China
Affordable and clean energy
Openalex Percentile: Top 50%
Nanowire Synthesis and Applications
0.18
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