Fault correcting adder design for low power applications

Field Programmable Gate Arrays are extensively used in space, military, and commercial sectors due to their reprogrammable nature. In high-safety environments, ensuring fault tolerance is crucial to improving the performance of electronic and computational systems. Common fault-tolerant methods include time redundancy, double modular redundancy, triple modular redundancy, hardware redundancy, self-checking, self-repairing, and Operand Width Aware Hardware Reuse. This paper introduces a novel approach based on error correction and detection techniques, aimed at reducing hardware complexity while optimizing for low power consumption, high speed, and minimal transistor count. The proposed technique is applicable to various arithmetic circuits. Fault-correcting and fault-detecting adders were designed using a combination of components, including a full adder (comprising one XOR gate, one NOT gate, and two 2:1 multiplexers), three XOR gates, three XNOR gates, one functional unit, two inverters, and two multiplexers (2:1 MUX). To assess the fault tolerance of the design, the technique was applied to an adder circuit, with its performance in terms of power consumption, hardware usage, energy efficiency, and delay simulated using Cadence Virtuoso @90 nm technology. Pre-layout and post-layout simulation results showed a 98% reduction in power consumption, 82% energy savings, 36.5 and 55.95% transistor savings, and a 215% reduction in area overhead compared to existing fault-tolerant adders. Additionally, multiplier designs were tested to validate the fault-correcting adder design.