AlphaAccelerator: An Automatic Neural FPGA Accelerator Design Framework Based on GNNs

This work introduces AlphaAccelerator, a graph neural network-based approach to developing an FPGA accelerator designed to optimize the inference performance of deep neural networks. We train a pair of neural networks one of which embeds a neural architecture into a latent vector (encoder). The other one generates a corresponding hardware architecture from the latent vector (decoder), which is optimized for a certain FPGA. In this way, we can fully automate the process of building a highly efficient neural accelerator. Evaluation results show that hardware accelerators made by our method demonstrate higher performance with less resource consumption compared to the existing works.