A Low-power PLL with a Standby Mode

This paper presents a phase-locked loop (PLL) with a standby mode to achieve a low power consumption at 0.6 V. The multi-band self-calibration circuit (MSCC) obtains a small VCO gain for the jitter performance. In standby mode, a power switch circuit is adopted to obtain a low leakage current. The test chip of PLL is designed in a 90nm CMOS process. The chip area and core area are 978×641 and 531×204 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, respectively. The power consumption, at 915 MHz, is 213 uW under the supply voltage of 0.6 V. In the standby mode, the power consumption of the PLL is 19 nW.