Production-Oriented Design for High Parallel Test Efficiency

As the importance and complexity of System-on-Chip (SoC) testing increase, research to enhance test efficiency is being conducted. Among these, research is ongoing to reduce the number of pins used in testing through internal test modules in the Device Interface Board (DIB) application area. However, the existing test modules were designed without considering the actual mass production environment, making them unsuitable for application in the actual chip fabrication process. In this paper, we propose a method that offers enhanced error detection capabilities and high parallelism, implementing additional functionalities required for mass production, making it applicable to actual manufacturing processes.