Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor

Screening for frequency-dependent failures that comprise a significant proportion of Silent Data Errors (SDE) in microprocessors is addressed using timing-aware scan tests. Silicon experiments targeting SDE-sensitive modules in the Core of a recent data center product is performed using such tests. Vmin measurements with these tests demonstrate the promise of this approach.