LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets

Single-Event Double-Node Upsets (SEDUs) increasingly compromise the integrity of storage cells like latches or flip-flops, especially as technology scales down to sub-65nm nodes. Traditional RHBD (Radiation-Hardened by Design) strategies, such as DICE and TMR, crafted to counter Single-Event Node Upset (SEU), are proving to be inadequate to SEDU. Consequently, recent research suggests the use of expanded areas to shield circuits from SEDUs, yet this often results in disproportional overhead. In response, the LESER methodology emerged as an effective measure, introducing minimal redundancy while still guaranteeing full SEDU resilience. However, having mitigated SEDUs across different latches within ASAP7 (a predictive process), LESER calls for further improvement in three pivotal issues: (1) spacing impact, (2) dummy gates, and (3) device configuration. Thus, LESER-2 has been developed, targeting these three challenges in latches designed with two industrial process nodes. LESER-2 presents a dual-level architecture, encompassing both device and circuit strata. At the device level, LESER-2 replaces the virtual process model card with industrial ones, significantly enhancing simulation accuracy concerning heavy ion impacts on transistors. Additionally, circuit-level layout modification within LESER-2 are meticulously calibrated to mitigate SEDUs in vulnerable node pairs. Empirical tests validate the LESER-2 modifications applied to latches under two industrial process nodes, accomplishing a 100% rate of soft error prevention while incurring an average area overhead of 16.5%, effectively resolving the three aforementioned issues.