Delay Monitoring Under Different PVT Corners for Test and Functional Operation

The adverse effects of silent data errors (SDEs) on the operation of large data centers have been reported recently by hyper-scalar companies. SDEs tend to be elusive and are difficult to detect until they affect a particular application after the IC has been deployed in-field. Although the cause of SDEs ranges from manufacturing test escapes and design marginalities to design bugs, experimental data from the industry largely indicate that SDEs can be traced back to timing related issues that become more severe with aging and depend on the operating conditions of process, voltage and temperature (PVT). This paper describes a complete framework for monitoring the timing related issues under different operating conditions for test and functional operation. The framework has three components. The first component is a procedure for the identification of the longest paths that are prone to delay failures under different PVT corners. The second component is a programmable slack monitor design that monitors the changes in path delays within a detection window, and produces an alarm when a path is close to failure, with proximity to failure being a programmable feature. The third component is a procedure that determines the placement of the monitors in the design. Experimental results for an industrial design demonstrate the trade-offs related to the placement of monitors and the scenarios under which the monitors raise alarms.