22/16nm High Speed and Area Efficient Automotive Grade STT-MRAM Memory Compiler for 2~128Mb

Automotive grade 2~128Mb embedded MRAM compiler was developed for 22/16nm technologies and supports 64/128/256 I/O options. New compiling flow with advanced EDA tools is allowing to develop MRAM with significant reduction of the design cycles, and highest accuracy. Implemented new concept of the resistive sourceline mitigates bitcells leakage influence on to the read at high temperature operation. Presented write driver concept designed to support high write current at lower voltage headroom. It compensates critical drops over the bitline by using of non-MTJ mimic bitline. Driver provides digital output to the replica switches located in each I/O. Achieved area reduction of 0.6x~0.9x, and 5ns read access time.