Scan SerDes^* for Multi-die Packages

As multi-die chip packages gain popularity, testing dice without direct access to the package IO<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> presents a challenge. This paper describes a scan SerDes implementation [1] [2] designed to transfer test or scan data between the IO-die (the die with direct access to the package IO) and core-dice (other function-specific dice within the package) of a multi-die package. The key objective is to keep the implementation transparent to ATPG<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> tools, allowing it to be viewed as a fixed number of pipeline stages, thereby minimizing programming overhead for ATPG patterns. Additionally, this approach enables wafer sort structural test patterns to be re-used at the package test stage without modification. Our solution is especially well-suited for multi-die packages with narrow die-to-die interconnect links, where the limited bandwidth can become a bottleneck for parallel test data transfer.