Automated Design of CMOS-DACML Circuit

This paper presents a new method for designing a differential amplifier using CMOS technology, incorporating a current mirror load (CMOS-DACML). To tackle the intricate optimization challenges presented by this nonlinear and multidimensional problem, the study utilizes a combined optimization strategy called fitness-based adaptive differential evolution with particle swarm optimization (ADEPSO). Through this hybrid approach, the design achieves substantial enhancements across critical performance metrics. Specifically, it achieves a notable reduction in power dissipation, lowering it to 520.60 µW. Moreover, the amplifier demonstrates a higher gain of 44.70 dB, significantly reduced output capacitance of 4.20 pF, and an enhanced cutoff frequency reaching 103.60 kHz. These outcomes highlight the effectiveness of ADEPSO in tackling the intricate challenges associated with differential amplifier design, especially in the context of CMOS-DACML. By optimizing these parameters simultaneously, the approach not only improves performance metrics but also underscores its potential for future applications in integrated circuit design and optimization.

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Publication Details

Published
2024-09-19
DOI
https://doi.org/10.1109/iicccs61609.2024.10763693
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
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Abstract

This paper presents a new method for designing a differential amplifier using CMOS technology, incorporating a current mirror load (CMOS-DACML). To tackle the intricate optimization challenges presented by this nonlinear and multidimensional problem, the study utilizes a combined optimization strategy called fitness-based adaptive differential evolution with particle swarm optimization (ADEPSO). Through this hybrid approach, the design achieves substantial enhancements across critical performance metrics. Specifically, it achieves a notable reduction in power dissipation, lowering it to 520.60 µW. Moreover, the amplifier demonstrates a higher gain of 44.70 dB, significantly reduced output capacitance of 4.20 pF, and an enhanced cutoff frequency reaching 103.60 kHz. These outcomes highlight the effectiveness of ADEPSO in tackling the intricate challenges associated with differential amplifier design, especially in the context of CMOS-DACML. By optimizing these parameters simultaneously, the approach not only improves performance metrics but also underscores its potential for future applications in integrated circuit design and optimization.

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