Hardware-aware Network Compression for Hybrid Vision Transformer via Low-Rank Approximation

In recent years, transformer-based models have achieved excellent performance in various fields such as computer vision and language processing. Specifically, vision transformer (ViT) models outperform conventional convolutional neural networks (CNNs) in image classification tasks by achieving higher accuracy. However, ViT-based models often require more parameters than CNNs, making efficient deployment challenging in memory-constrained environments such as mobile devices. For example, the peak memory required in the output header layer of EfficientViT was 39.32 Mb. Deploying such a layer on the Zynq-7000 XC7Z045 FPGA board requires off-chip memory access, leading to inefficient power consumption. To address these issues, we applied a low-rank approximation method to reduce the memory requirements of the EfficientViT-B1 model. Our proposed method using the EfficientViT-B1 model on the ImageNet dataset achieved performance with only a 0.43% accuracy drop without requiring DRAM access.

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Publication Details

Published
2024-08-19
DOI
https://doi.org/10.1109/isocc62682.2024.10762117
Primary Topic
CCD and CMOS Imaging Sensors
Type
article
Field-Weighted Citation Impact
0.00

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article

Hardware-aware Network Compression for Hybrid Vision Transformer via Low-Rank Approximation

Hyun Kim, Beom Jin Kang, Nam Joon Kim
CCD and CMOS Imaging Sensors
article

Hardware-aware Network Compression for Hybrid Vision Transformer via Low-Rank Approximation

Hyun Kim, Beom Jin Kang, Nam Joon Kim
article en

Abstract

In recent years, transformer-based models have achieved excellent performance in various fields such as computer vision and language processing. Specifically, vision transformer (ViT) models outperform conventional convolutional neural networks (CNNs) in image classification tasks by achieving higher accuracy. However, ViT-based models often require more parameters than CNNs, making efficient deployment challenging in memory-constrained environments such as mobile devices. For example, the peak memory required in the output header layer of EfficientViT was 39.32 Mb. Deploying such a layer on the Zynq-7000 XC7Z045 FPGA board requires off-chip memory access, leading to inefficient power consumption. To address these issues, we applied a low-rank approximation method to reduce the memory requirements of the EfficientViT-B1 model. Our proposed method using the EfficientViT-B1 model on the ImageNet dataset achieved performance with only a 0.43% accuracy drop without requiring DRAM access.

Seoul National University of Science and Technology (KR)
National Research Foundation
Affordable and clean energy
Openalex Percentile: Top 81%
CCD and CMOS Imaging Sensors
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