Write Bias Scheme Optimization of Ferroelectric Field-Effect-Transistor (FeFET) Synapse for Accurate On-chip Training

Through technology computer-aided-design (TCAD) simulation and ferroelectric capacitor measurement, we optimized the write bias scheme in on-chip training of HfO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>-based ferroelectric field-effect-transistor (FeFET) synapse to improve training accuracy. With the optimized write bias scheme secured in this work, 4-bit synaptic operation was confirmed even in the presence of D2D variations in remanent polarization (P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</inf>) and coercive field (E<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</inf>) induced by the ferroelectric film process and the wake-up procedure.