MBIST-based MRAM defect screening for safety-critical applications

Testing magnetoresistive random access memory (MRAM) presents several challenges, particularly in scaled technology nodes. One major challenge is the increased interconnect resistance from the bitline and sourceline, which leads to issues like the near-far effect, where bitcells farther from the sensing circuit exhibit higher resistance. Additionally, the fabrication process can result in defects that may not be easily detectable using conventional testing methods. Another factor that makes the screening process more difficult is the presence of process variation. This paper proposes a memory-built-in self-test (MBIST) compatible method that compensates for the interconnect resistance effect using multi-level references and memory partitioning. In addition, the proposed method aims to find the location in the memory array that is less affected by process variation and use it to adjust the screening boundaries for the entire memory to detect defective bitcells more effectively. On average, the proposed method shows around 50% defect coverage improvement and 76% weak bitcell coverage improvement over its previous counterparts. The detected defects will be further evaluated for repair by ECC or other redundancy schemes to maximize product quality and yield.