Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs

Choosing a DfT architecture for heterogeneous multi-core SoCs is constrained by various business, design and industrial-test requirements. SSN is a bus-based packetized data distribution scan architecture designed to address these requirements. A comparison between SSN and previous hierarchical DfT approaches is shown. A specific project SoC requirements is reviewed with packetized scan delivery architecture trade-offs. Results show 2X scan data transfer rate while adhering to pinning, area and physical design constraints.

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Publication Details

Published
2024-11-03
DOI
https://doi.org/10.1109/itc51657.2024.00020
Citations
1
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
0.49
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article

Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs

Mahmoud AbdAlwahab, Hiroyuki Iwata, Ron Press, Ohki Sugiura
1 citations
VLSI and Analog Circuit Testing
0.49
article

Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs

Mahmoud AbdAlwahab, Hiroyuki Iwata, Ron Press, Ohki Sugiura
article en
1 citations

Abstract

Choosing a DfT architecture for heterogeneous multi-core SoCs is constrained by various business, design and industrial-test requirements. SSN is a bus-based packetized data distribution scan architecture designed to address these requirements. A comparison between SSN and previous hierarchical DfT approaches is shown. A specific project SoC requirements is reviewed with packetized scan delivery architecture trade-offs. Results show 2X scan data transfer rate while adhering to pinning, area and physical design constraints.

Siemens (Netherlands) (NL), Siemens (United States) (US), Renesas Electronics (Japan) (JP)
Industry, innovation and infrastructure
Openalex Percentile: Top 34%
VLSI and Analog Circuit Testing
0.49
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