Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs
Choosing a DfT architecture for heterogeneous multi-core SoCs is constrained by various business, design and industrial-test requirements. SSN is a bus-based packetized data distribution scan architecture designed to address these requirements. A comparison between SSN and previous hierarchical DfT approaches is shown. A specific project SoC requirements is reviewed with packetized scan delivery architecture trade-offs. Results show 2X scan data transfer rate while adhering to pinning, area and physical design constraints.
Authors
- Mahmoud AbdAlwahab
- Hiroyuki Iwata (ORCID: https://orcid.org/0000-0002-0475-8519)
- Ron Press (ORCID: https://orcid.org/0000-0001-6855-0568)
- Ohki Sugiura
Institutions
- Siemens (Netherlands) (NL)
- Siemens (United States) (US)
- Renesas Electronics (Japan) (JP)
Publication Details
- Published
- 2024-11-03
- DOI
- https://doi.org/10.1109/itc51657.2024.00020
- Citations
- 1
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.49