Timing Analysis with Analytical Sensitivity

Timing analysis is the backbone of all VLSI designs. It is the only performance evaluation tool capable of dealing with complete designs and is thus the gateway to finalizing a design. Timing Analysis relies on a simple abstraction of the operation of digital circuits into gates and waveforms. Timing simulators and analyzers work by propagating events from the circuits inputs to the output. Post-simulation analysis can identify timing faults, such as setup or hold violations, as well as the longest critical path in the circuit. In this work, we extend this paradigm to include the analytical sensitivity of timing to gate sizes. This sensitivity can then be used to optimize timing via gate sizing, including the impact of each gate on the overall circuit rather than on each circuit path.