A 1.08pJ/bit DisplayPort RX with Combined AFE Offset Cancellation and Training-Less Link Setup

This paper presents a 0.5~5.4-Gbps, 1.08-pJ/bit receiver (RX) for DisplayPort (DP) V1.2 with an improved rotational frequency detector which permits link setup without training sequence. Adaptive offset compensation realized by a feedback OTA is combined with foreground calibration for the offset of AFE (including the slicer and continuous-time linear equalizer (CTLE)). Programmable CTLE and clock data recovery (CDR) circuits with quad-mode phase detection scheme ensure the wide range of data rate with optimum power consumption. Fabricated in 40-nm CMOS, occupying an active area of 0.144 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, the RX output shows a total jitter of 51 ps for 5.4-Gb/s input with BER=10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup>. The competitive power efficiency of 1.03 pJ/bit/lane is measured with a supply voltage of 1.1 V.