Digital Scan and ATPG for Analog Circuits

Scan-based automatic test pattern generation (ATPG) is commonly used for ‘random logic’ in ICs, but there is no equivalent for analog/mixed-signal (AMS) circuits due to their diversity of functions, stimuli, and responses. As a result, tests are written manually on the intended automatic test equipment (ATE) with (possibly defective) ‘first silicon’ devices, typically requiring months of effort and test times higher than for the digital circuitry. Proving the defect coverage of these tests in simulation is typically impractical, and <80% when it can be simulated. This paper describes a structural, scan-based design-for-test (DfT) and ATPG technique for ‘random analog’ that has minimal area and performance impact. The tests can be applied by digital ATE and IEEE 1687 (IJTAG) networks. Results show that automatically generated tests for a 4<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup>-order filter, bandgap + voltage regulator, 8-bit DAC, and industrial 11-bit SAR ADC achieve comparable or higher coverage of IEEE P2427-specified shorts and opens, relative to specification tests, in <1 ms. Defect coverage can be simulated in <1 hour, fast enough to verify before tape-out.