A Resilient All-Digital PLL Using Ping-Pong Delay Line

This paper presents an innovative All-Digital Phase Locked Loop (ADPLL) with a robust delay line configuration that enhances system resilience across changing environmental conditions. The proposed ADPLL integrates a pair of delay lines, called ping-pong delay lines, allowing a wide frequency tracking range without compromising the integrity of the loop operation. Under the VDD-changing scenario, which includes a voltage drop from 1V to 0.97V within 15 microseconds, the ADPLL demonstrated consistent performance, highlighting its potential for hostile operating conditions. The proposed ADPLL has an area of 0.04mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and its output clock frequency ranges from 0.45GHz to 1.45GHz, consuming 3.49mW of power at 1GHz. With the prosed Ping-Pong scheme, we could achieve a 29.5% peak-to-peak jitter reduction when compared with our baseline ADPLL under a VDD-changing scenario in five corners, 25°C.