Integration of IP-Cores for the M³ Architecture with Low Area Overhead: Accelerator Support Module

Smart digital systems are integral to sectors such as communications, power grids, and autonomous transport. As these technologies increasingly underpin critical societal functions, the need for robust, breach-resistant security architectures becomes paramount. Secure tiled architectures with stringent hardware isolation capabilities have been shown to have a minimized attack surface even when integration of third-party intellectual property (IP) cores is indicated. However, current platforms require costly adaption of IP cores to the security protocols these architectures provide. This paper introduces a new Accelerator Support Module that manages the protocol overhead of the underlying security architecture and offers commonly used hardware interfaces. This module simplifies the integration of accelerators and only slightly increases the area overhead.