A Low-Noise Capacitively-Coupled Chopper Instrumentation Amplifier with SAR-Assisted Low Current Ripple Reduction Technique

This paper presents a novel design technique for reducing ripple in various sensor read-out integrated circuits (IC) by calibrating the amplifier offset through current control in bias resistors. Traditional methods for reducing ripple often involve complex amplifiers consuming static power. In contrast, the proposed ripple reduction technique employs successive-approximation register (SAR) logic to control the current flowing through the bias resistor, thus minimizing static power consumption. Experimental results obtained through simulations in a 28 nm CMOS process demonstrate significant ripple reduction to 8.94 μV<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</inf> from 2 mV<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</inf>. This approach is suitable for low-power design, particularly in wearable device applications, and can potentially extend to other amplifier configurations utilizing chopping technique.