AI-Assisted Design Automation of Circular and Asymmetric Inductor in CMOS Technology

This paper presents a methodology of the automated inductor generator for radio-frequency (RF) integrated circuit. We propose a machine learning assisted parameterized-cell (PCELL) generation method. This method supports polygonal, circular and asymmetric inductor shapes. The proposed PCELL has been validated in 65-nm CMOS 1P9M process and analyzed in terms of inductance (L), quality factor (Q factor) and area. An artificial-neural-network (ANN) based regression model is trained to reduce the EM based inductor design cost such as ×530 less simulation time. According to the target inductor design optimization, 1 GHz operating frequency, we achieve the relative error rates of 0.63% and 1.73% for L and Q factor, respectively.

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Publication Details

Published
2024-08-19
DOI
https://doi.org/10.1109/isocc62682.2024.10762371
Citations
2
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
Field-Weighted Citation Impact
0.42

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article

AI-Assisted Design Automation of Circular and Asymmetric Inductor in CMOS Technology

D. H. Kim, Kyung‐Sik Choi, Jin-Won Hyun, Jae-Won Nam
2 citations
Advancements in Semiconductor Devices and Circuit Design
0.42
article

AI-Assisted Design Automation of Circular and Asymmetric Inductor in CMOS Technology

D. H. Kim, Kyung‐Sik Choi, Jin-Won Hyun, Jae-Won Nam
article en
2 citations

Abstract

This paper presents a methodology of the automated inductor generator for radio-frequency (RF) integrated circuit. We propose a machine learning assisted parameterized-cell (PCELL) generation method. This method supports polygonal, circular and asymmetric inductor shapes. The proposed PCELL has been validated in 65-nm CMOS 1P9M process and analyzed in terms of inductance (L), quality factor (Q factor) and area. An artificial-neural-network (ANN) based regression model is trained to reduce the EM based inductor design cost such as ×530 less simulation time. According to the target inductor design optimization, 1 GHz operating frequency, we achieve the relative error rates of 0.63% and 1.73% for L and Q factor, respectively.

Seoul National University of Science and Technology (KR)
Ministry of Education, National Research Foundation
Industry, innovation and infrastructure
Openalex Percentile: Top 36%
Advancements in Semiconductor Devices and Circuit Design
0.42
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